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87C196CB 20 mhz advanced 16-bit chmos microcontroller with integrated can 2.0 automotive production datasheet product features 1. 16 mhz standard; 20 mhz is speed premium. n C40c to +125c ambient n high performance chmos 16-bit cpu n up to 56 kbytes of on-chip eprom n up to 1.5 kbyte of on-chip register ram n up to 512 bytes of additional ram (code ram) n register-register architecture n 8 channel/10-bit a/d with sample/hold n 38 prioritized interrupts n up to seven 8-bit (56) i/o ports n full duplex serial i/o port with dedicated baud rate generator n interprocessor communication slave port n oscillator fail detection circuitry n 15 message objects of 8 bytes data length n up to 16 mbyte linear address space n high speed peripheral transaction server (pts) n two dedicated 16-bit high-speed compare registers n 10 high speed capture/compare (epa) n full duplex synchronous serial i/o port (ssio) n two flexible 16-bit timer counters n flexible 8-/16-bit external bus (programmable) n programmable bus (hld/hlda) n 1.4 s 16 x 16 multiply n 2.4 s 32/16 divide n 20 mhz operation 1 n supports can (controller area network) specification 2.0 order no: 272405-006 october 1998 notice: this document contains information on products in full production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design.
87C196CB - automotive ii production datasheet information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 87C196CB - automotive may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtain ed from: intel corporation po box 5937 denver co 80217-9808 call 1-800-548-4725 copyright ? intel corporation 7/8/97 *third-party brands and names are the property of their respective owners.
production datasheet iii 87C196CB - automotive contents 1.0 introduction ................................................................................................................ ... 1 2.0 block diagram............................................................................................................... 2 3.0 process information ......................................................................................................3 4.0 pin descriptions ............................................................................................................ 6 5.0 electrical characteristics.............................................................................................10 5.1 dc characteristics ........................................................................................ 10 5.1.1 87C196CB - automotive additional bus timing modes ................... 12 5.1.1.1 mode 3............................................................................... 12 5.1.1.2 mode 0............................................................................... 12 5.2 ac characteristics......................................................................................... 12 5.2.1 test conditions ................................................................................ 12 5.2.2 87C196CB - automotive timings ..................................................... 15 5.2.3 87C196CB timings .......................................................................... 16 5.2.4 87C196CB - automotive timings ..................................................... 17 5.2.5 87C196CB - automotive ac characteristics - slave port ................ 18 5.2.6 explanation of ac symbols.............................................................. 22 5.3 eprom specifications .................................................................................. 23 5.3.1 ac eprom programming characteristics....................................... 23 5.3.2 eprom programming waveforms .................................................. 24 5.4 ac characteristics - serial port - shift register mode.................................. 26 5.4.1 a/d characteristics........................................................................... 27 5.4.1.1 a/d converter specification ................................................ 27 6.0 datasheet revision history.........................................................................................30
87C196CB - automotive iv production datasheet figures 1 87C196CB - automotive block diagram ..........................................................2 2 the 87C196CB - automotive family nomenclature ........................................3 3 84-pin plcc an87C196CB diagram ..............................................................4 4 100-pin qfp as87C196CB diagram ..............................................................5 5 chip configuration registers ...........................................................................9 6 87C196CB i cc vs frequency .........................................................................11 7 87C196CB - automotive system bus timing ................................................15 8 87C196CB - automotive ready timings (one wait state)............................16 9 87C196CB buswidth timings ........................................................................16 10 87C196CB hold#/holda# timings............................................................17 11 slave port waveform - (slpl = 0).................................................................18 12 slave port waveform - (slpl = 1).................................................................19 13 synchronous serial port ................................................................................20 14 external clock drive waveforms ...................................................................21 15 input/output test conditions .........................................................................21 16 float test conditions .....................................................................................22 17 slave programming mode data program mode with single program pulse .24 18 slave programming mode in word dump or data verify mode with auto increment .......................................................................................24 19 slave programming mode timing in data program mode with repeated program pulse and auto increment .......................................25 20 waveform - serial port - shift register mode ................................................26 21 ad_time 1fafh:byte ...................................................................................27 tables 1 device overview ..............................................................................................1 1 thermal characteristics ...................................................................................3 2 pin descriptions ...............................................................................................6 3 87C196CB memory map..................................................................................8 4 dc characteristics (under listed operating conditions)...............................10 5 ac characteristics (over specified operating conditions)............................12 6 ac characteristics (over specified operating conditions)............................14 7 8xc196cb hold#/holda# timings (over specified operation conditions)17 8 slave port timing - (slpl = 0, 1, 2, 3) ..........................................................18 9 slave port timing - (slpl = 1, 2, 3) ..............................................................19 10 normal master/slave operation.....................................................................20 11 handshake operation ....................................................................................20 12 external clock drive.......................................................................................21 13 explanation of ac symbols............................................................................22 14 ac eprom programming characteristics.....................................................23 15 dc eprom programming characteristics ....................................................23 16 serial port timing - shift register mode........................................................26 17 10-bit mode a/d operating conditions ..........................................................27 18 10-bit mode a/d characteristics (using above operating conditions) (1) ....28 19 8-bit mode a/d operating conditions ............................................................28 20 8-bit mode a/d characteristics (using above operating conditions) (1) ......29
production datasheet 1 87C196CB - automotive 1.0 introduction the 87C196CB - automotive is a member of the mcs ? 96 microcontroller family. this device is based upon the mcs 96 kx/jx microcontroller product families with enhancements ideal for automotive and industrial applications. the 87C196CB - automotive is the first device in the kx family to support networking through the integration of the can 2.0 (controller area network) peripheral on-chip. the 87C196CB offers the highest memory density of the mcs 96 microcontroller family, with 56k of on-chip eprom, 1.5k of on-chip register ram, and 512 bytes of additional ram (code ram). in addition, the 87C196CB provides up to 16 mbyte of linear address space. table 1. device overview device pins/ package eprom reg ram code ram i/o epa sio ssio can a/d addr space 87C196CB 84-pin plcc 56k 1.5k 512b 56 10 y y y 8 1 mbyte 87C196CB 100-pin qfp 56k 1.5k 512b 60 10 y y y 8 16 mbyte
87C196CB - automotive 2 production datasheet 2.0 block diagram the mcs 96 microcontroller family members are all high-performance microcontrollers with a 16-bit cpu. the 87C196CB is composed of the high-speed (20 mhz) macrocore with up to 16 mbyte linear address space, 56 kbytes of program eprom, up to 1.5 kbytes of register ram, and up to 512 bytes of code ram (16-bit addressing modes) with the ability to execute from this ram space. it supports the high-speed, serial communications protocol can 2.0, with 15 message objects of 8 bytes data length, an 8-channel, 10-bit / 3 lsb analog to digital converter with programmable s/h times, and conversion times < 15 m s at 20 mhz. it has an asynchronous/synchronous serial i/o port (sio) with a dedicated 16-bit baud rate generator, an additional synchronous serial i/o port (ssio) with full duplex master/slave transceivers, a flexible timer/counter structure with prescaler, cascading, and quadrature capabilities. there are ten modularized, multiplexed, high-speed i/o for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs, and a sophisticated prioritized interrupt structure with programmable peripheral transaction server (pts) implementing several channel modes, including single/burst block transfers from any memory location to any memory location, a pwm and pwm toggle mode to be used in conjunction with the epa, and an a/d scan mode. figure 1. 87C196CB - automotive block diagram a4606-01 a/d converter sync serial port and baud gen watchdog timer event processor array alu 16 cpu microcode engine interrupt controller 512 bytes internal ram 56k on-chip eprom (optional) peripheral transaction server memory controller 1.5k byte register file s/h mux port 0 serial port baud rate gen port 6 port 1 port 2 can 2.0 timer 1 timer 2 queue port 6 ssio a/d port 0 port 1 epa port 2 / hold control rxcan txcan port 5 control signals port 3 ad0-7 port 4 ad8-15 eport a16-23 v ref angnd 16 8
production datasheet 3 87C196CB - automotive 3.0 process information these devices are manufactured on p629.5, a chmos iii-e process. additional process and reliability information is available in intel's components quality and reliability handbook , order number 210997. all thermal impedance data is approximate for static air conditions at 1 w of power dissipation. values change depending on operation conditions and application. see the intel packaging handbook (order number 240800) for a description of intel's thermal impedance test methodology. figure 2. the 87C196CB - automotive family nomenclature table 1. thermal characteristics device and package q ja q jc an87C196CB (84-lead plcc package) 35c/w 11c/w notes: 1. q ja = thermal resistance between junction and the surrounding environment (ambient) measurements are taken 1 ft. away from case in air flow environment. q jv = thermal resistance between junction and package face (case). 1. all values of q ja and q jc may fluctuate depending on the environment (with or without airflow, and how much airflow) 1. and device power dissipation at temperature of operation. typical variations are 2c/w. 1. values listed are at a maximum power dissipation of 1 w. a4610-01 ax 87 cc 20 b 196 frequency designation: 20 = 20 mhz no mark = 16 mhz 7 = eprom, otp product designation product family chmos technology program memory options: n = plcc (plastic leaded chip carrier) s = qfp (quad flatpack) package type options: a = -40 ? c to +125 ? c ambient with intel standard burn-in temperature and burn-in options:
87C196CB - automotive 4 production datasheet figure 3. 84-pin plcc an87C196CB diagram a4548-01 pllen p6.3 / t1dir p6.2 / t1clk p6.1 / epa9 p6.0 / epa8 p1.0 / epa0 p1.1 / epa1 p1.2 / epa2 p1.3 / epa3 p1.4 / epa4 p1.5 / epa5 p1.6 / epa6 p1.7 / epa7 v ss1 v cc v ref agnd p0.7 / ach7 p0.6 / ach6 p0.5 / ach5 p0.4 / ach4 p5.2 / wr# p5.5 /bhe# p5.3 / rd# v pp p5.0 / ale p5.1 / inst p5.6 / ready p5.4 / slpint ep3.3 / a19 v cc v ss1 v ss rxcan txcan xtal1 xtal2 p6.7 / sd1 p6.6 / sc1 p6.5 / sd0 p6.4 / sc0 v cc p5.7 / busw ep3.1 / a17 ep3.0 / a16 p4.7 / ad15 p4.6 / ad14 p4.5 / ad13 p4.4 / ad12 p4.3 / ad11 p4.2 / ad10 p4.1 / ad9 p4.0 / ad8 v ss1 v cc p3.7 / ad7 p3.6 / ad6 p3.5 / ad5 p3.4 / ad4 p3.3 / ad3 p3.2 / ad2 p3.1 / ad1 ep3.2 / a18 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 an87C196CB 84-lead plcc view of component as mounted on pc board 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p3.0 / ad0 reset# nmi ea# v ss1 v cc v ss p2.0 / txd p2.1 / rxd p2.2 / extint p2.3 / intb# p2.4 / intintout# p2.5 / hld# p2.6 / hlda# p2.7 / clkout v cc v ss1 p0.0 / ach0 p0.1 / ach1 p0.2 / ach2 p0.3 / ach3 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
production datasheet 5 87C196CB - automotive figure 4. 100-pin qfp as87C196CB diagram a6076-01 p5.7 / buswidth p5.2 / wr# / wrl# p5.5 / bhe# / wrh# p5.3 / rd# a20 / eport.4 a21 / eport.5 a22 / eport.6 v pp a23 / eport.7 p5.0 / adv# / ale p5.1 / inst / slpcs# p5.6 / ready p5.4 / slpint a19 / eport.3 nc v cc nc v ss1 v ss nc rxcan txcan xtal1 xtal2 nc p6.7 / sd1 p6.6 / sc1 p6.5 / sd0 p6.4 / sc0 v cc ad18 / eport.2 ad1 / p3.1 ad2 / p3.2 ad3 / p3.3 ad4 / p3.4 ad5 / p3.5 ad6 / p3.6 ad7 / p3.7 v cc v ss1 ad8 / p4.0 ad9 / p4.1 ad10 / p4.2 ad11 / p4.3 ad12 / p4.4 ad13 / p4.5 ad14 / p4.6 ad15 / p4.7 a16 / eport.0 a17 / eprot.1 nc ad0 / p3.0 reset# nmi ea# v ss1 nc v cc nc v ss nc nc nc nc p2.0 / txd p2.1 / rxd p2.2 / extint p2.3 / breq# nc p2.4 / intout# p2.5 / hold# p2.6 / hlda# / once# p2.7 / clkout v cc v ss1 p0.0 / ach0 p0.1 / ach1 p0.2 / ach2 p0.3 / ach3 p0.4 / ach4 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 as87C196CB view of component as mounted on pc board 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p0.5 / ach5 p0.6 / ach6 p0.7 / ach7 angnd v ref v cc v ss1 p1.7 / epa7 p1.6 / epa6 p1.5 / epa5 p1.4 / epa4 p1.3 / epa3 p1.2 / epa2 / t2dir p1.1 / epa1 p1.0 / epa0 / t2clk p6.0 / epa8 / comp0 p6.1 / epa9 / comp1 p6.2 / t1clk p6.3 / t1dir pllen 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
87C196CB - automotive 6 production datasheet 4.0 pin descriptions table 2. pin descriptions (sheet 1 of 2) name description v cc main supply voltage (+5 v). v ss , v ss1 digital circuit ground (0 v). there are seven v ss pins, all of which must be connected to a single ground plane. v ref reference for the a/d converter (+5 v). v ref is also the supply voltage to the analog portion of the a/d converter and the logic used to read port 0. must be connected for a/d and port 0 to function. v pp programming voltage for the eprom parts. it should be +12.5 v for programming. it is also the timing pin for the return from powerdown circuit. connect this pin with a 1 f capacitor to v ss and a 1 m w resistor to v cc . if this function is not used, v pp may be tied to v cc . angnd reference ground for the a/d converter. must be held at nominally the same potential as v ss . xtal1 input of the oscillator inverter and the internal clock generator. xtal2 output of the oscillator inverter. reset# reset input to the chip. input low for at least 16 state times resets the chip. the subsequent low-to-high transition resynchronizes clkout and commences a 10-state time sequence in which the psw is cleared, bytes are read from 2018h, 201ah and 201ch (if enabled) loading the ccbs, and a jump to location 2080h is executed. input high for normal operation. reset# has an internal pullup. nmi a positive transition causes a non-maskable interrupt vector through memory location 203eh. if not used, this pin should be tied to v ss . may be used by intel evaluation boards. ea# input for memory select (external access). ea# equal to a high causes memory accesses to locations 0ff2000h through 0fffffh to be directed to on-chip eprom/rom. ea# equal to a low causes accesses to these locations to be directed to off- chip memory. ea# = +12.5 v causes execution to begin in the programming mode. ea# latched at reset. pllen selects between pll mode or pll bypass mode. this pin must be either tied high or low. pllen pin = 0, bypass pll mode. pllen pin = 1, places a 4x pll at the input of the crystal oscillator. allows for a low frequency crystal to drive the device (i.e., 5 mhz = 20 mhz operation). p6.4-6.7/ssio dual-function i/o ports that have a system function as synchronous serial i/o. two pins are clocks and two pins are data, providing full duplex capability. also, lsio when not used as ssio. p6.3/t1dir dual-function i/o pin. primary function is that of a bidirectional i/o pin, however, it may also be used as a timer1 direction input. the timer1 increments when this pin is high and decrements when this pin is low. p6.2/t1clk dual-function i/o pin. primary function is that of a bidirectional i/o pin, however may also be used as a timer1 clock input. the timer1 increments or decrements on both positive and negative edges of this pin. p6.0-6.1/epa8-9 dual-function i/o port pins. primary function is that of bidirectional i/o. system function is that of high speed capture and compare. p5.7/buswidth input for bus width selection. if ccr bit 1 is a one and ccr1 bit 2 is a one, this pin dynamically controls the buswidth of the bus cycle in progress. if buswidth is low, an 8-bit cycle occurs, if buswidth is high, a 16-bit cycle occurs. if ccr bit 1 is 0 and ccr1 bit 2 is 1, all bus cycles are 8-bit, if ccr bit 1 is 1 and ccr1 bit 2 is 0, all bus cycles are 16-bit. ccr bit 1 = 0 and ccr1 bit 2 = 0 is illegal. also an lsio pin when not used as buswidth. p5.6/ready ready input to lengthen external memory cycles, for interfacing with slow or dynamic memory, or for bus sharing. if the pin is high, cpu operation continues in a normal manner. if the pin is low prior to the falling edge of clkout, the memory controller goes into a wait state mode until the next positive transition in clkout occurs with ready high. when external memory is not used, ready has no effect. the max number of wait states inserted into the bus cycle is controlled by the ccr/ccr1. also an lsio if ready is not selected.
production datasheet 7 87C196CB - automotive p5.5/bhe#/wrh# byte high enable or write high output, as selected by the ccr. bhe# = 0 selects the bank of memory that is connected to the high byte of the data bus. a0 = 0 selects the bank of memory that is connected to the low byte. thus accesses to a 16-bit wide memory can be to the low byte only (a0 = 0, bhe# = 1), to the high byte only (a0 = 1, bhe# = 0) or both bytes (a0 = 0, bhe# = 0). if the wrh# function is selected, the pin goes low if the bus cycle is writing to an odd memory location. bhe#/wrh# is only valid during 16-bit external. also an lsio pin when not bhe/wrh#. p5.4/slpint dual-function i/o pin. as a bidirectional port pin or as a system function. the system function is a slave port interrupt output pin. p5.3/rd# read signal output to external memory. rd# is active only during external memory reads or lsio when not used as rd#. p5.2/wr#/wrl# write and write low output to external memory, as selected by the ccr, wr# goes low for every external write, while wrl# goes low only for external writes where an even byte is being written. wr#/wrl# is active during external memory writes. also an lsio pin when not used as wr#/wrl#. p5.1/inst output high during an external memory read indicates the read is an instruction fetch. inst is valid throughout the bus cycle. inst is active only during external memory fetches, during internal eprom fetches inst is held low. also lsio when not inst. p5.0/ale/adv# address latch enable or address valid output, as selected by ccr. both pin options provide a latch to demultiplex the address from the address/data bus. when the pin is adv#, it goes inactive (high) at the end of the bus cycle. adv# can be used as a chip select for external memory. ale/adv# is active only during external memory accesses. also lsio when not used as ale. port3 and 4 8-bit bidirectional i/o ports with open drain outputs. these pins are shared with the multiplexed address/data bus which has strong internal pullups. p2.7/clkout output of the internal clock generator. the frequency is the oscillator frequency. clkout has a 50% duty cycle. also lsio pin when not used as clkout. p2.6/hlda# bus hold acknowledge. active-low output indicates that the bus controller has relinquished control of the bus. occurs in response to an external device asserting the hld# signal. also lsio when not used as hlda#. p2.5/hld# bus hold. active-low signal indicates that an external device is requesting control of the bus. also lsio when not used as hld#. p2.4/intout# interrupt output. this active-low output indicates that a pending interrupt requires use of the external bus. also lsio when not used as intout#. p2.3/breq# bus request. this active-low output signal is asserted during a hold cycle when the bus controller has a pending external memory cycle. also lsio when not used as breq#. p2.2/extint a positive transition on this pin causes a maskable interrupt vector through memory location 203ch. also lsio when not used as extint. p2.1/rxd receive data input pin for the serial i/o port. also lsio if not used as rxd. p2.0/txd transmit data output pin for the serial i/o port. also lsio if not used as txd. port 1/epa0C7 dual-function i/o port pins. primary function is that of bidirectional i/o. system function is that of high speed capture and compare. epa0 and epa2 have another function of t2clk and t2dir of the timer2 timer/counter. port 0/ach0C7 8-bit high impedance input-only port. these pins can be used as digital inputs and/or as analog inputs to the on-chip a/d converter. these pins are also used as inputs to eprom parts to select the programming mode. eport 8-bit bidirectional standard and i/o port. these bits are shared with the extended address bus, a16Ca19 for cb plcc, a16Ca23 for cb qfp. pin function is selected on a per pin basis. txcan push-pull output to the can bus line. rxcan high impedance input-only from the can bus line. table 2. pin descriptions (sheet 2 of 2) name description
87C196CB - automotive 8 production datasheet table 3. 87C196CB memory map address description notes ffffffh ff2080h program memory - internal eprom or external memory (determined by ea# pin) ff207fh ff2000h special purpose memory - internal eprom or external memory (determined by ea# pin) ff1fffh ff0600h external memory ff05ffh ff0400h internal ram (identically mapped into 00400hC005ffh) ff03ffh ff0100h external memory ff00ffh ff0000h reserved for ice feffffh 0f0000h overlaid memory (external)-accesses into memory ranges 0f0000h to feffffh will overlay page 15 (0fh) for cb qfp package-external memory. (5) 0effffh 010000h 900 kbytes external memory 00ffffh 002080h external memory or remapped otprom (program memory) (1) 00207fh 002000h external memory or remapped otprom (special purpose memory) (1,3) 001fffh 001fe0h memory mapped special function registers (sfr's) 001fdfh 001f00h internal peripheral special function registers (sfr's) (5) 001effh 001e00h internal can peripheral memory (5) 001dffh 001c00h internal register ram 001bffh 000600h external memory 0005ffh 000400h internal ram (code ram) (address with indirect or indexed modes) 0003ffh 000100h register ram C upper register file (address with indirect or indexed modes or through windows.) (2) 0000ffh 000018h register ram C lower register file. (address with direct, indirect, or indexed modes.) (2) 000017h 000000h cpu sfr's (4) notes: 1. these areas are mapped internal eprom if the remap bit (ccb2.2) is set and ea# = 5 v. otherwise they are external memory. 2. code executed in locations 0000h to 003ffh is forced external. 3. reserved memory locations must contain 0ffh unless noted. 4. reserved sfr bit locations must be written with 0. 5. refer to 8xc196cb supplement to 8xc196nt user's manual for sfr, can and paging descriptions.
production datasheet 9 87C196CB - automotive figure 5. chip configuration registers ccb (2018h : byte) 0 1 2 3 4 5 6 7 pd bw0 wr ale irc0 irc1 loc0 loc1 = = = = = = = = 1 enables powerdown see table 1 = wr#/bhe - 0 = wrl#/wrh# 1 = ale - 0 = adv } see table } see table ccb1 (201ah : byte) 0 1 2 3 4 5 6 7 ccr2 irc2 bw1 wde 1 0 memsel0 memsel1 = = = = = = = = 1 fetch ccb2 see table see table 0 = always enabled reserved must be 1 reserved must be 0 see table see table loc1 loc0 function irc2 irc1 irc0 max wait states 0 0 1 1 0 1 0 1 read and write protected write protected only read protected only no protection 0 1 1 1 1 0 0 0 1 1 0 0 1 0 1 zero wait states 1 wait state 2 wait states 3 wait states infinite msel1 msel0 cb bus timing mode bw1 bw0 bus width 0 0 1 1 0 1 0 1 mode 0 (1-wait kr) reserved reserved mode 3 (kr) 0 0 1 1 0 1 0 1 illegal 16-bit only 8-bit only bw pin controlled mode 0 (1-wait kr): designed to be similar to the 87c196kr bus timing with 1 automatic wait state. see ac timings section for actual timings data. mode 3 (kr): designed to be similar to the 87c196kr bus timing. see ac timings section for actual timings data. ccb2 (201ch : byte) 0 1 2 3 4 5 6 7 0 mode16 remap 1 1 1 1 1 = = = = = = = = reserved must be 0 select 16-bit or 24-bit mode 0Cselect eprom/coderam in segment 0ffh only 1Cselect both segment 0ffh and segment 00h reserved must be 1 reserved must be 1 reserved must be 1 reserved must be 1 reserved must be 1 }
87C196CB - automotive 10 production datasheet 5.0 electrical characteristics 5.1 dc characteristics absolute maximum ratings* storage temperature C60c to +150c voltage from v pp or ea# to v ss or angnd ............................... C0.5 v to +13.0 v voltage from any other pin to v ss or angnd ............................... C0.5 v to +7.0 v this includes v pp on rom and cpu devices. power dissipation................................. 1.0 w operating conditions t a (ambient temperature under bias) ..... C40c to +125c v cc (digital supply voltage) 4.75 v to 5.25 v v ref (analog supply voltage) 4.75 v to 5.25 v f osc (oscillator frequency ..................... 4 mhz to 20 mhz note: angnd and v ss should be nominally at the same potential. notice: this is a production data sheet. the specifi- cations are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. *warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. table 4. dc characteristics (under listed operating conditions) (sheet 1 of 2) symbol parameter min typ max units test conditions i cc v cc supply current (C40c to +125c ambient) 100 ma xtal1 = 20 mhz v cc = v pp = v ref = 5.25 v (while device in reset) i ref a/d reference supply current 5ma i idle idle mode current 35 ma xtal1 = 20 mhz v cc = v pp = v ref = 5.25 v i pd powerdown mode current 50 a v cc = v pp = v ref = 5.52 v (notes 5,8) v il input low voltage (all pins) C0.5 0.3 v cc v for port0 (note 7) v ih input high voltage 0.7 v cc v cc + 0.5 v for port0 (note 7) v ol output low voltage (outputs configured as complementary) 0.3 0.45 1.5 v i ol = 200 a (note 3) i ol = 3.2 ma i ol = 7 ma v oh output high voltage (output configured as complementary) v cc C 0.3 v cc C 0.7 v cc C 1.5 v i oh = C200 a (note 3) i oh = C3.2 ma i oh = C7 ma i li input leakage current (standard inputs) 10 a v ss < v in < v cc notes: 1. all bd (bidirectional) pins except inst and clkout. inst and clkout are excluded due to not being weakly pulled high in reset. bd pins include port1, port2, port3, port4, port5 and port6 except slpint (p5.4) and hlda# (p2.6). 2. standard input pins include xtal1, ea#, reset# and port 1/2/5/6 when setup as inputs. 3. all bidirectional i/o pins when configured as outputs (push/pull). 4. device is static and should operate below 1 hz, but only tested down to 4 mhz. 5. typicals are based on limited number of samples and are not guaranteed. the values listed are at room temperature and v ref = v cc = 5 v. 6. violating these specifications in reset may cause the device to enter test mode (p5.4 and p2.6). 7. when p0 is used as analog inputs, refer to a/d specifications for this characteristic. 8. for temperatures < 100c typical is 10 a.
production datasheet 11 87C196CB - automotive i li1 input leakage current (port 0) 1 a v ss < v in < v ref v oh1 slpint (p5.4) and hlda# (p2.6) output high voltage in reset# 2vi oh = 0.8 ma (note 6) v oh2 output high voltage in reset# v cc C 1 v i oh = C15 a (note 1) c s pin capacitance (any pin to v ss ) 10 pf f test = 1 mhz (note 5) r rst reset pullup resistor 65 k 180 k w r wpu weak pullup resistance 150 k w (note 5) figure 6. 87C196CB i cc vs frequency table 4. dc characteristics (under listed operating conditions) (sheet 2 of 2) symbol parameter min typ max units test conditions notes: 1. all bd (bidirectional) pins except inst and clkout. inst and clkout are excluded due to not being weakly pulled high in reset. bd pins include port1, port2, port3, port4, port5 and port6 except slpint (p5.4) and hlda# (p2.6). 2. standard input pins include xtal1, ea#, reset# and port 1/2/5/6 when setup as inputs. 3. all bidirectional i/o pins when configured as outputs (push/pull). 4. device is static and should operate below 1 hz, but only tested down to 4 mhz. 5. typicals are based on limited number of samples and are not guaranteed. the values listed are at room temperature and v ref = v cc = 5 v. 6. violating these specifications in reset may cause the device to enter test mode (p5.4 and p2.6). 7. when p0 is used as analog inputs, refer to a/d specifications for this characteristic. 8. for temperatures < 100c typical is 10 a. a5863-01 active i cc max = 100 ma active i cc = 83 ma idle max = 35 ma idle i cc = 28 ma 100 90 80 70 60 50 40 30 20 10 0 2 8 14 20 i cc = [ma]
87C196CB - automotive 12 production datasheet 5.1.1 87C196CB - automotive additional bus timing modes the 87C196CB - automotive device has two bus timing modes for external memory interfacing. 5.1.1.1 mode 3 mode 3 is the standard timing mode. use this mode for systems that emulate the 87c196kr bus timings. 5.1.1.2 mode 0 mode 0 is the standard timing mode, but 1 (minimum) wait state is always inserted in external bus cycles. 5.2 ac characteristics 5.2.1 test conditions ? capacitive load on all pins = 100 pf ? rise and fall times = 10 ns table 5. ac characteristics (over specified operating conditions) (sheet 1 of 2) symbol parameter min max units the 87C196CB - automotive will meet these specifications f xtal frequency on xtal1 420mhz (1) t osc xtal1 period (1/f xtal ) 50 250 ns t xhch xtal1 high to clkout high or low 20 110 ns t ofd clock failure to reset pulled low 440 s (6) t clcl clkout period 2t osc ns (2) t chcl clkout high period t osc C10 t osc +15 ns t cllh clkout low to ale/adv high C15 10 ns t llch ale/adv# low to clkout high C20 15 ns t lhlh ale/adv# cycle time 4t osc ns (2,5) t lhll ale/adv# high time t osc C10 t osc +10 ns t av l l address valid to ale low t osc C15 ns t llax address hold after ale/adv# low t osc C40 ns notes: 1. testing performed at 4 mhz, however, the device is static by design and typically operates below 1 hz. 2. typical specifications, not guaranteed. 3. assuming back-to-back bus cycles. 4. 8-bit bus only. 5. if wait states are used, add 2t osc x n = number of wait states. if mode 0 (1 automatic wait state added) operation is selected, add 2t osc to specification. 6. t ofd is the time for the oscillator fail detect circuit (ofd) to react to a clock failure. the ofd circuitry is enabled by programming the uprom location 0778h with the value 0004h. programming the cde bit enables oscillator fail detection.
production datasheet 13 87C196CB - automotive t llrl ale/adv# low to rd# low t osc C30 ns t rlcl rd low to clkout low C8 20 ns t rlrh rd# low period t osc C10 ns (5) t rhlh rd# high to ale/adv# high t osc t osc +25 ns (3) t rlaz rd# low to address float 5 ns t llwl ale/adv# low to wr# low t osc C10 ns t clwl clkout low to wr# low C5 25 ns t qvwh data valid before wr# high t osc C23 ns t chwh clkout high to wr# high C10 15 ns t wlwh wr# low period t osc C20 ns (5) t whqx data hold after wr# high t osc C25 ns t whlh wr# high to ale/adv# high t osc C10 t osc +15 ns (3) t whbx bhe#, inst hold after wr# high t osc C10 ns t whax ad8-15 hold after wr# high t osc C30 ns (4) t rhbx bhe#, inst hold after rd# high t osc C10 ns t rhax ad8-15 hold after rd# high t osc C30 ns (4) table 5. ac characteristics (over specified operating conditions) (sheet 2 of 2) symbol parameter min max units notes: 1. testing performed at 4 mhz, however, the device is static by design and typically operates below 1 hz. 2. typical specifications, not guaranteed. 3. assuming back-to-back bus cycles. 4. 8-bit bus only. 5. if wait states are used, add 2t osc x n = number of wait states. if mode 0 (1 automatic wait state added) operation is selected, add 2t osc to specification. 6. t ofd is the time for the oscillator fail detect circuit (ofd) to react to a clock failure. the ofd circuitry is enabled by programming the uprom location 0778h with the value 0004h. programming the cde bit enables oscillator fail detection.
87C196CB - automotive 14 production datasheet table 6. ac characteristics (over specified operating conditions) symbol parameter min max units the system must meet these specifications to work with the 87C196CB - automotive t avyv address valid to ready setup 2 t osc C75 ns (3) t llyv ale low to ready setup 2 t osc C70 ns (3) t ylyh non ready time no upper limit ns t clyx ready hold after clkout low 0t osc C30 ns (1) t av g v address valid to buswidth setup 2 t osc C75 ns (2,3) t llgv ale low to buswidth setup t osc C60 ns (2,3) t clgx buswidth hold after clkout low 0 ns t av dv address valid to input data valid 3t osc C55 ns (2) t rldv rd# active to input data valid t osc C30 ns (2) t cldv clkout low to input data valid t osc C50 ns t rhdz end of rd# to input data float t osc ns t rhdx data hold after rd# high 0 ns notes: 1. if maximum is exceeded, additional wait states will occur. 2. if wait states are used, add 2 t osc x n, where n = number of wait states. 3. if mode 0 is selected, one wait state minimum is always added. if additional wait states are required, add 2 t osc to the specification.
production datasheet 15 87C196CB - automotive 5.2.2 87C196CB - automotive timings figure 7. 87C196CB - automotive system bus timing a5874-01 xtal1 clkout ale / adv# rd# wr# t osc t xhch t clcl t cllh t llch t lhlh t lhll t llrl t rldv t rlaz address out a0 C a15 address out data out data in t wlwh bus read bus write bhe, inst valid address out ad8Cad15 valid 8-bit bus mode if mode 0 operation is selected, add 2 t osc to this time. bhe#, inst ad8Cad15 t avll t avdv t llwl t rlrh t llax t rhlh t rhdx t rhdz t qvwh t whqx t whax or t rhax t whbx or t rhbx
87C196CB - automotive 16 production datasheet 5.2.3 87C196CB timings figure 8. 87C196CB - automotive ready timings (one wait state) figure 9. 87C196CB buswidth timings a5876-01 clkout ale ready rd# bus read address out wr# bus write t llch t cllh t clcl t xhch xtal1 t osc t llyv t avyv t clyx (max) t clyx (min) t rlrh + 2 t osc t rhdx t avdv + 2 t osc data in address out t wlwh + 2 t osc t qvwh + 2 t osc data out if mode 0 selected, one wait state is always added. if additional wait states are required, add 2 t osc to these specifications. a5875-01 clkout ale bus width bus write xtal1 t osc t llgv t clgx t avgv valid valid address out address out data out if mode 0 selected, add 2 t osc to these specifications.
production datasheet 17 87C196CB - automotive 5.2.4 87C196CB - automotive timings table 7. 8xc196cb hold#/holda# timings (over specified operation conditions) symbol parameter min max units t hvch hold setup time 65 ns (1) t clhal clkout low to hlda low C15 15 ns t clbrl clkout low to breq low C15 15 ns t azhal hlda low to address float 20 ns t bzhal hlda low to bhe#, inst, rd#, wr# weakly driven 25 ns t clhah clkout low to hlda high C15 15 ns t clbrh clkout low to breq high C25 25 ns t hahax hlda high to address no longer float C15 ns t hahbv hlda high to bhe#, inst, rd#, wr# valid C10 15 ns note: 1. to guarantee recognition at next clock. figure 10. 87C196CB hold#/holda# timings a5848-01 clkout hold# holda# breq# bus bhe#, inst, rd#, wr# ale t chlh t clhah t clbrh t hahax t hahax t halbz t halaz t clbrl t clhal t hvch t hvch t osc hold latency
87C196CB - automotive 18 production datasheet 5.2.5 87C196CB - automotive ac characteristics - slave port figure 11. slave port waveform - (slpl = 0) table 8. slave port timing - (slpl = 0, 1, 2, 3) symbol parameter min max units t savwl address valid to wr# low 50 ns t srhav rd# high to address valid 60 ns t srlrh rd# low period t osc ns t swlwh wr# low period t osc ns t srldv rd# low to output data valid 60 ns t sdvwh input data setup to wr# high 20 ns t swhqx wr# high to data invalid 30 ns t srhdz rd# high to data float 15 ns note: 1. test conditions: ?f osc = 20 mhz ?t osc = 60 ns ? rise/fall time = 10 ns ? capacitive pin load = 100 pf 2. these values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. a5847-01 cs ale / a1 rd p3 wr t swlwh t srldv t srhav t savwl t srlrh t sdvwh t swhqx t srhdz
production datasheet 19 87C196CB - automotive figure 12. slave port waveform - (slpl = 1) table 9. slave port timing - (slpl = 1, 2, 3) symbol parameter min max units t selll cs# low to ale low 20 ns t srheh rd# or wr# high to cs# high 60 ns t sllrl ale low to rd# low t osc ns t srlrh rd# low period t osc ns t swlwh wr# low period t osc ns t savll address valid to ale low 20 ns t sllax ale low to address invalid 20 ns t srldv rd# low to output data valid 60 ns t sdvwh input data setup to wr# high 20 ns t swhqx wr# high to data invalid 30 ns t srhdz rd# high to data float 15 ns note: 1. test conditions: ?f osc = 20 mhz ?t osc = 60 ns ? rise/fall time = 10 ns ? capacitive pin load = 100 pf 2. these values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. a5846-01 cs ale rd p3 wr t srldv t swlwh t sllrl t selll t srheh t srlrh t savll t sllax t sdvwh t swhqx t srhdz
87C196CB - automotive 20 production datasheet table 10. normal master/slave operation symbol parameter min (1) max units t chch clock period 4t ns t clch clock low time/clock high time 2tC10 ns t cldv clock falling to data out valid (master) 0.5t 1.5t + 20 ns t cldv1 clock falling to data out valid (slave) 0.5t 1.5t + 50 ns t dvch data in setup to clock rising edge 10 ns t chdx clock rising edge to data in invalid t + 15 ns note: 1. t = 1 state time (100 ns @ 20 mhz). 2. timings are guaranteed by design. table 11. handshake operation symbol parameter min (1) max units t chch clock period 4t ns t clch clock low time/clock high time 2tC10 ns (2) t cldv clock falling to data out valid (master) 0.5t 1.5t + 20 ns t cldv1 clock falling to data out valid (slave) 0.5t 1.5t + 20 ns t dvch data in setup to clock rising edge 10 ns t chdx clock rising edge to data in invalid t + 15 ns note: 1. t = 1 state time (100 ns @ 20 mhz). 2. this specification refers to input clocks during slave operation. during master operation, the device outputs a nominal 50% duty cycle clock. figure 13. synchronous serial port a4512-01 d5 d4 d3 d2 msb d6 d1 d0 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 sc x (normal transfers) sd x (out) sd x (in) sc x (handshaking transfers) slave receiver pulls sc x low t clcl t clch ste bit t d1dv t cxdx t cxdv t dvcx t dxcx valid valid valid valid valid valid valid valid
production datasheet 21 87C196CB - automotive table 12. external clock drive symbol parameter min (1) max units 1/t xlxl oscillator frequency 4 20 mhz t xlxl oscillator period (t osc )50250ns t xhxx high time 0.35 t osc 0.65 t osc ns t xlxx low time 0.35 t osc 0.65 t osc ns t xlxh rise time 10 ns t xhxl fall time 10 ns figure 14. external clock drive waveforms figure 15. input/output test conditions t xlxx a5842-01 t xhxx t xhxl t xlxl 0.3 v cc C 0.5 v 0.7 v cc + 0.5 v t xlxh 0.7 v cc + 0.5 v 0.3 v cc C 0.5 v 0.7 v cc + 0.5 v test points 2.0 v 0.8 v note: ac testing inputs are driven at 3.5 v for a logic 1 and 0.45 v for a logic 0 . timing measurements are made at 2.0 v for a logic 1 and 0.8 v for a logic 0. 3.5 v 0.45 v a5843-01 inputs outputs
87C196CB - automotive 22 production datasheet 5.2.6 explanation of ac symbols each symbol is two pairs of letters prefixed by t for time. the characters in a pair indicate a signal and its condition, respectively. symbols represent the time between the two signal/condition points. figure 16. float test conditions v load v load C 0.15 v v load + 0.15 v timing reference points v oh C 0.15 v v ol + 0.15 v note: for timing purposes, a port pin is no longer floating when a 150 mv change from load voltage occurs and begins to float when a 150 mv change from the loading v oh /v ol level occurs with i ol /i oh 15 ma. a5844-01 table 13. explanation of ac symbols conditions signals h C high a C address ha C hlda# l C low b C bhe# l C ale/adv# v C valid br C breq# q C data out x C no longer valid c C clkout r C rd# z C floating d C data w C wr#/wrh#/wri# g C buswidth x C xtal1 h C hold# y C ready
production datasheet 23 87C196CB - automotive 5.3 eprom specifications 5.3.1 ac eprom programming characteristics operating conditions: ? load capacitance = 150 pf ?t c = 25c 5c ?v ref = 5.0 v 0.25 v ?v cc = 5.0 v 0.25 v ? angnd = 0 v ?v pp = 12.5 v 0.25 v ?v ss = 0 v ? ea# = 12.5 v 0.25 v ?f osc = 5.0 mhz table 14. ac eprom programming characteristics symbol parameter min max units t avll address setup time 0 t osc t llax address hold time 100 t osc t dvpl data setup time 0 t osc t pldx data hold time 400 t osc t lllh pale# pulse width 50 t osc t plph prog# pulse width (2) 100 t osc t lhpl pale# high to prog# low 220 t osc t phll prog# high to next pale# low 220 t osc t phdx word dump hold time 50 t osc t phpl prog# high to next prog# low 220 t osc t lhpl pale# high to prog# low 220 t osc t pldv prog# low to word dump valid 100 t osc t shll reset# high to first pale# low 1100 t osc t phil prog# high to ainc# low 0 t osc t ilih ainc# pulse width 240 t osc t ilvh pver hold after ainc# low 50 t osc t ilpl ainc# low to prog# low 170 t osc t phvl prog# high to pver# valid 220 t osc notes: 1. run time programming is done with f osc = 6 mhz to 10 mhz, v cc , v pd , v ref = 5 v 0.25 v, t c = 25c 5c and v pp = 12.5 v 0.25 v. for run-time programming over a full operating range, contact factory. 2. programming specifications are not tested, but guaranteed by design. 3. this specification is for the word dump mode. for programming pulses use 300 t osc + 100 s. table 15. dc eprom programming characteristics symbol parameter min max units i pp v pp programming supply current 200 ma note: v pp must be within 1 v of v cc while v cc < 4.5 v. v pp must not have a low impedance path to ground or v ss while v cc > 4.5 v.
87C196CB - automotive 24 production datasheet 5.3.2 eprom programming waveforms figure 17. slave programming mode data program mode with single program pulse figure 18. slave programming mode in word dump or data verify mode with auto increment ports 3/4 reset# address/command t avll data address/command t shll t lllh t dvpl t pldx prog# p2.2 pale# p2.1 t lhpl t plph t llax t phll pver# p2.0 t phvl valid t llvh a5838-01 ports 3/4 reset# address/command ver bits/wd dump t shll prog# p2.2 pale# p2.1 t pldv pver# p2.0 t ilpl addr addr + 2 t phdx t pldv t phdx ver bits/wd dump t a5839-01 phpl
production datasheet 25 87C196CB - automotive figure 19. slave programming mode timing in data program mode with repeated program pulse and auto increment ports 3/4 reset# address/command data prog# p2.2 pale# p2.1 t phpl pver# p2.0 t phil data p1 p2 valid for p1 t ilpl valid for p2 t ilvh t ilih ainc# p2.4 a5840-01
87C196CB - automotive 26 production datasheet 5.4 ac characteristics - serial port - shift register mode operating conditions: ? t a = C40c +125c ? v ss = 0.0 v ? v cc = 5.0 v 5% ? load capacitance = 100 pf table 16. serial port timing - shift register mode symbol parameter min max units t xlxl serial port clock period 8 t osc ns t xlxh serial port clock falling edge to rising edge 4 t osc C 50 4 t osc + 50 ns t qvxh output data setup to clock rising edge 3 t osc ns t xhqx output data hold after clock rising edge 2 t osc C 50 ns t xhqv next output data valid after clock rising edge 2 t osc + 50 ns t dvxh input data setup to clock rising edge 2 t osc + 200 ns t xhdx input data hold after clock rising edge 0 ns t xhqz last clock rising to output float 5t osc ns note: 1. parameters not tested. figure 20. waveform - serial port - shift register mode a5841-01 valid valid valid valid valid valid valid valid rxd x (in) txd x 01 2 3 4 5 6 7 t qvxh t xlxl t dvxh t xhqv t xhqz t xhdx t xhqx t xlxh rxd x (out)
production datasheet 27 87C196CB - automotive 5.4.1 a/d characteristics the sample and conversion time of the a/d converter in the 8-bit or 10-bit modes is programmed by loading a byte into the ad_time special function register. this allows optimizing the a/d operation for specific applications. the ad_time register is functional for all possible values, but the accuracy of the a/d converter is only guaranteed for the times specified in the operating conditions table. the value loaded into ad_time bits 5, 6, 7 determines the sample time, samp. the value loaded into ad_time bits 0, 1, 2, 3 and 4 determines the bit conversion time, conv. these bits, as well as the equation for calculating the total conversion time, t, are shown in figure 21 . the converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of v ref . v ref must be close to v cc since it supplies both the resistor ladder and the analog portion of the converter and input port pins. there is also an ad_test sfr that allows for conversion on angnd and v ref as well as adjusting the zero offset. the absolute error listed is without doing any adjustments. 5.4.1.1 a/d converter specification the specifications given assume adherence to the operating conditions section of this data sheet. testing is performed with v ref = 5.12 v and 20 mhz operating frequency. after a conversion is started, the device is placed in idle mode until the conversion is complete. figure 21. ad_time 1fafh:byte 0 7654321 (samp) 4n + 1 state times n = 1 to 7 (conv) n + 1 state times n = 2 to 31 equation: t = (samp) + bx (conv) + 2.5 t = total conversion time (states) b = number of bits conversion (8 or 10) n = programmed register value sample time bit conversion time table 17. 10-bit mode a/d operating conditions symbol parameter min max units t a ambient temperature C40 +125 c v cc digital supply voltage 4.75 5.25 v v ref analog supply voltage 4.75 5.25 v (1) t sam sample time 2 s (2) t conv conversion time 15 18 s (2) f osc oscillator frequency 4 20 mhz notes: 1. v ref must be within+0.5 v of v cc . 2. the value of ad_time is selected to meet these specifications.
87C196CB - automotive 28 production datasheet table 18. 10-bit mode a/d characteristics (using above operating conditions) (1) parameter typical (2,3) min max units (4) notes resolution 1024 10 1024 10 levels bits absolute error 0 3lsbs full-scale error 0.25 0.5 lsbs zero offset error 0.25 0.5 lsbs non-linearity 1 2 3lsbs differential non-linearity > C 0.75 + 0.75 lsbs channel-to-channel matching 0.1 0 1lsbs repeatability 0.25 0 lsbs (2) temperature coefficients: offset fullscale differential non-linearity 0.009 lsb/c (2) off isolation C 60 db (2,5,6) feedthrough C 60 db (2,5) v cc power supply rejection C 60 db (2,5) input resistance 750 1.2 k w (8) dc input leakage 1C 3 3 a voltage on analog input pin angnd C0.5 v ref + 0.25 v (7) sampling capacitor 3 pf notes: 1. all conversions performed with processor in idle mode. 2. these values are expected for most parts at 25c but are not tested or guaranteed. 3. these values are not tested in production and are based on theoretical estimates and/or laboratory test. 4. an lsb, as used here, has a value of approximately 5 mv 5. dc to 100 khz 6. multiplexer break-before-make guaranteed. 7. applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 8. resistance from device pin, through internal mux, to sample capacitor. table 19. 8-bit mode a/d operating conditions symbol parameter min max units t a ambient temperature C40 +125 c v cc digital supply voltage 4.75 5.25 v v ref analog supply voltage 4.75 5.25 v (1) t sam sample time 2 s (2) t conv conversion time 12 15 s (2) f osc oscillator frequency 4 20 mhz notes: 1. v ref must be within+0.5 v of v cc . 2. the value of ad_time is selected to meet these specifications.
production datasheet 29 87C196CB - automotive table 20. 8-bit mode a/d characteristics (using above operating conditions) (1) parameter typical (2,3) min max units (4) notes resolution 256 8 256 8 levels bits absolute error 0 1lsbs full-scale error 0.5 lsbs zero offset error 0.5 lsbs non-linearity 0 1lsbs differential non-linearity C 0.5 + 0.5 lsbs channel-to-channel matching 0 1lsbs repeatability 0.25 0 lsbs (2) temperature coefficients: offset fullscale differential non-linearity 0.003 lsb/c (2) off isolation C 60 db (2,5,6) feedthrough C 60 db (2,5) v cc power supply rejection C 60 db (2,5) input resistance 750 1.2 k w (8) dc input leakage 1 C 1.5 1.5 a voltage on analog input pin angnd C0.5 v ref + 0.25 v (7) sampling capacitor 3 pf notes: 1. all conversions performed with processor in idle mode. 2. these values are expected for most parts at 25c but are not tested or guaranteed. 3. these values are not tested in production and are based on theoretical estimates and/or laboratory test. 4. an lsb, as used here, has a value of approximately 5 mv 5. dc to 100 khz 6. multiplexer break-before-make guaranteed. 7. applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 8. resistance from device pin, through internal mux, to sample capacitor.
87C196CB - automotive 30 production datasheet 6.0 datasheet revision history this is the -006 revision of the 87C196CB - automotive datasheet. the following differences exist between the -005 and the -006 revision. 1. figure 4: added - p5.3/ to pin 77. removed p5.3/ from pin 76. 2. table 4 - v oh1 : changed - max value (was 2, now blank) to min value (was blank, now 2). this is the -005 revision of the 87C196CB - automotive datasheet. the following differences exist between the -004 and the -005 revision. 1. converted to new template. 2. corrected grammar. 3. moved first page talbe and text paragraph to introduction section. 4. changed operating supply voltage specifications from 10% to 5%. 5. removed all references to 87c196ca from data sheet. 6. changed from advance information to production data sheet. this is the -003 revision of the 87C196CB - automotive data sheet. the following differences exist between the -002 version and the -003 revision. 1. the data sheet has been revised to advance from preliminary, indicating the specifications have been verified through electrical tests. 2. the 87C196CB 100-ld qfp package and device pinout has been added to the data sheet. 3. the 87C196CB 100-ld qfp device supports up the 16 mbyte of linear address space. 4. the package thermal characteristics for the plcc packages was added to the data sheet, for the cb q ja = 35.0c/w, q jc = 11.0c/w. for the ca, q ja = 36.5c/w and q ja = 10.0c/w. 5. the an87C196CB pin package diagram was corrected to show ea# as opposed to ea. 6. the remap bit function for ccb2 was corrected. setting this bit to 0 selects eprom/coderam in segment 0ffh only. setting this bit to 1 selects both segment 0ffh and segment 00h. 7. t rlaz has been changed to 5 ns from 20 ns. 8. t wlwh for the ca has been changed to t osc C20 from t osc C30. 9. t clgx has been changed to 0 ns min, from t osc C46 max. 10. . timing specifications for the ssio are now added. these timings are currently guaranteed by design. 11. . added frequency designation to family nomenclature figure 2. this is the -002 revision of the 87c196ca data sheet. the following difference exist between the -001 version and the -002 revision. 1. this data sheet now includes the specifications for the 87C196CB as well as the 87c196ca. 2. absolute maximum ratings have been added. 3. maximum frequency has been increased to 20 mhz. 4. maximum i cc has been increased from 75 ma to 100 ma for the cb, 90 ma for the ca. 5. idle mode current has been increased to 35 ma from 30 ma for the cb, 40 ma for the ca.
production datasheet 31 87C196CB - automotive 6. input leakage current for port 0 (i li1 ) was decreased to 1.5 a from 2.0 a for the ca. 7. the electrical characteristics for the can module were removed. the electrical characteristics for txcan and rxcan are identical to standard port pins. 8. t osc (1/freq) was modified to reflect 20 mhz timings. 9. t ofd (oscillator fail detect specification) for clock failure to reset pin pulled low, was added to the data sheet (4 s min, 40 s max) 10. t whqx has been increased to t osc C25 ns min from t osc C30 ns min. 11. t rxdx has been replaced by t rhdx . t rlaz has been increased to 20 ns max from 5 ns max. 12. i pp programming supply current has been increased to 200 ma from 100 ma. 13. t conv conversion time for 10 bit a/d conversions has been decreased to reflect 20 mhz operation. 14. r rst was added for the 87c196ca, min = 6 k w /max = 65 k w . 15. t cllh Cmin/max parameters switched to accurately reflect this timing parameter. 16. t rlcl Cseparate timings for the 87c196ca vs 87C196CB. t rlcl for the cb is min C8 ns, max +20 ns. for the ca, t rlcl min +4 ns/max +30 ns. 17. t rlrh changed to t osc C10 ns from t osc C5 ns. 18. t av g v added for the 87C196CB. 19. t llgv added for the 87C196CB. 20. t clgx added for the 87C196CB. 21. t rldv Cseparate timings for 87C196CB.t rldv max = t osc C30 ns. for the 87c196ca, t rldv max = t osc C 22 ns. 22. hold/holda timings added for the 87C196CB. 23. slave port timings added for the 87C196CB. 24. separate specifications for t plph for the 87C196CB, t plph , min = 100 t osc . for the 87c196ca, t plph min = 50 t osc . 25. separate specifications for t pldv for the 87C196CB, t pldv min = 100 t osc for the 87c196ca, t pldv min = 50 t osc . 26. 8-bit mode a/d characteristics added.

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